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8 Mbit Firmware Hub
SST49LF008A
SST49LF008A8 Mb Firmware Hub for Intel 8xx Chipsets
Data Sheet
FEATURES:
* Firmware Hub for Intel 8xx Chipsets * 8 Mbit SuperFlash memory array for code/data storage - 1024K x8 * Flexible Erase Capability - Uniform 4 KByte Sectors - Uniform 64 KByte overlay blocks - 64 KByte Top Boot Block protection - Chip-Erase for PP Mode Only * Single 3.0-3.6V Read and Write Operations * Superior Reliability - Endurance:100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption - Active Read Current: 6 mA (typical) - Standby Current: 10 A (typical) * Fast Sector-Erase/Byte-Program Operation - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Byte-Program Time: 14 s (typical) - Chip Rewrite Time: 15 seconds (typical) - Single-pulse Program or Erase - Internal timing generation * Two Operational Modes - Firmware Hub Interface (FWH) Mode for In-System operation - Parallel Programming (PP) Mode for fast production programming * Firmware Hub Hardware Interface Mode - 5-signal communication interface supporting byte Read and Write - 33 MHz clock frequency operation - WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block - Block Locking Register for all blocks - Standard SDP Command Set - Data# Polling and Toggle Bit for End-of-Write detection - 5 GPI pins for system design flexibility - 4 ID pins for multi-chip selection * Parallel Programming (PP) Mode - 11-pin multiplexed address and 8-pin data I/O interface - Supports fast In-System or PROM programming for manufacturing * CMOS and PCI I/O Compatibility * Packages Available - 32-lead PLCC - 32-lead TSOP (8mm x 14mm) - 40-lead TSOP (10mm x 20mm) - Non-Pb (lead-free) packages available * All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST49LF008A flash memory devices are designed to be read-compatible with the Intel 82802 Firmware Hub (FWH) device for PC-BIOS application. These devices provide protection for the storage and update of code and data in addition to adding system design flexibility through five general purpose inputs. Two interface modes are supported by the SST49LF008A: Firmware Hub (FWH) Interface mode for in-system programming and Parallel Programming (PP) mode for fast factory programming of PC-BIOS applications. The SST49LF008A flash memory devices are manufactured with SST's proprietary, high performance SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST49LF008A devices significantly improve performance and reliability, while lowering power consumption.
(c)2006 Silicon Storage Technology, Inc. S71161-11-000 3/06 1
The SST49LF008A devices write (Program or Erase) with a single 3.0-3.6V power supply. They use less energy during Erase and Program than alternative flash memory technologies. The total energy consumed is a function of the applied voltage, current and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter Erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies. The SST49LF008A products provide a maximum ByteProgram time of 20 sec. The entire memory can be erased and programmed byte-by-byte typically in 15 seconds when using status detection features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology provides fixed Erase and Program times independent of the number of Erase/ Program cycles performed. Therefore the system software
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation. These specifications are subject to change without notice.
8 Mbit Firmware Hub SST49LF008A
Data Sheet or hardware does not have to be calibrated or correlated to the cumulated number of Erase/Program cycles as is necessary with alternative flash memory technologies, whose Erase and Program time increase with accumulated Erase/ Program cycles. To protect against inadvertent write, the SST49LF008A devices employ hardware and software data (SDP) protection schemes. It is offered with typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. To meet high density, surface mount requirements, the SST49LF008A devices are offered in a 32-lead TSOP package. In addition, the SST49LF008A is offered in 32lead PLCC and 40-lead TSOP packages. See Figures 2, 3, and 4 for pin assignments and Table 1 for pin descriptions.
TABLE OF CONTENTS
PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 LIST OF TABLES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DEVICE MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PRODUCT IDENTIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 MODE SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FIRMWARE HUB (FWH) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Firmware Hub Interface Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Abort Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Response To Invalid Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Device Memory Hardware Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data# Polling (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General Purpose Inputs Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Locking Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Lock Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 JEDEC ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
(c)2006 Silicon Storage Technology, Inc. S71161-11-000 3/06
2
8 Mbit Firmware Hub SST49LF008A
Data Sheet PARALLEL PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Byte-Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sector-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SOFTWARE COMMAND SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Characteristics (FWH Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC Characteristics (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PRODUCT ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PACKAGING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
(c)2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
3
8 Mbit Firmware Hub SST49LF008A
Data Sheet
LIST OF FIGURES
FIGURE 1: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FIGURE 2: Pin Assignments for 32-lead TSOP (8mm x 14mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 3: Pin Assignments for 32-lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FIGURE 4: Pin Assignments for 40-lead TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FIGURE 5: Device Memory Map for SST49LF008A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 FIGURE 6: Single-Byte Read Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 FIGURE 7: Write Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FIGURE 8: CLK Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FIGURE 9: Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FIGURE 10: Output Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FIGURE 11: Input Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FIGURE 12: Reset Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FIGURE 13: Read Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 FIGURE 14: Write Cycle Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FIGURE 15: Data# Polling Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FIGURE 16: Toggle Bit Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FIGURE 17: Byte-Program Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FIGURE 18: Sector-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FIGURE 19: Block-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FIGURE 20: Chip-Erase Timing Diagram (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FIGURE 21: Software ID Entry and Read (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 FIGURE 22: Software ID Exit and Reset (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIGURE 23: AC Input/Output Reference Waveforms (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIGURE 24: A Test Load Example (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIGURE 25: Byte-Program Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FIGURE 26: Wait Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 FIGURE 27: Software Product Command Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 FIGURE 28: Erase Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FIGURE 29: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH . . . . . . . . . . . . . . . . . . . . 39 FIGURE 30: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH . . . . . . 40 FIGURE 31: 40-lead Thin Small Outline Package (TSOP) 10mm x 20mm SST Package Code: EI . . . . . . 41
(c)2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
4
8 Mbit Firmware Hub SST49LF008A
Data Sheet
LIST OF TABLES
TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 3: FWH Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 4: FWH Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 5: General Purpose Inputs Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 6: Block Locking Registers for SST49LF008A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TABLE 7: Block Locking Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TABLE 8: Operation Modes Selection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 TABLE 9: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 10: DC Operating Characteristics (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TABLE 11: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TABLE 12: Pin Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TABLE 13: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TABLE 14: Clock Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TABLE 15: Read/Write Cycle Timing Parameters, VDD =3.0-3.6V (FWH Mode) . . . . . . . . . . . . . . . . . . . . 24 TABLE 16: AC Input/Output Specifications, VDD =3.0-3.6V (FWH Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 24 TABLE 17: Reset Timing Parameters, VDD =3.0-3.6V (FWH Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TABLE 18: Interface Measurement Condition Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TABLE 19: Read Cycle Timing Parameters, VDD =3.0-3.6V (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TABLE 20: Program/Erase Cycle Timing Parameters, VDD =3.0-3.6V (PP Mode) . . . . . . . . . . . . . . . . . . 27 TABLE 21: Reset Timing Parameters, VDD =3.0-3.6V (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TABLE 22: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
(c)2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
TBL# WP# INIT#
X-Decoder
FWH[3:0] CLK FWH4 ID[3:0] FGPI[4:0] R/C# A[10:0] DQ[7:0] OE# WE#
SuperFlash Memory
FWH Interface
Address Buffers & Latches Y-Decoder
Control Logic
I/O Buffers and Data Latches
Programmer Interface
IC RST#
1161 B1.2
FIGURE 1: Functional Block Diagram
(c)2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
6
8 Mbit Firmware Hub SST49LF008A
Data Sheet
PIN ASSIGNMENTS
NC NC NC VSS (VSS) IC (IC) A10 (FGPI4) R/C# (CLK) VDD (VDD) NC RST# (RST#) A9 (FGPI3) A8 (FGPI2) A7 (FGPI1) A6 (FGPI0) A5 (WP#) A4 (TBL#)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Standard Pinout Top View Die Up
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1161 32-tsop P1.0
OE# (INIT#) WE# (FWH4) VDD (VDD) DQ7 (RES) DQ6 (RES) DQ5 (RES) DQ4 (RES) DQ3 (FWH3) VSS (VSS) DQ2 (FWH2) DQ1 (FWH1) DQ0 (FWH0) A0 (ID0) A1 (ID1) A2 (ID2) A3 (ID3)
( ) Designates FWH Mode
FIGURE 2: Pin Assignments for 32-lead TSOP (8mm x 14mm)
RST# (RST#)
A7(FGPI1) A6 (FGPI0) A5 (WP#) A4 (TBL#) A3 (ID3) A2 (ID2) A1 (ID1) A0 (ID0) DQ0 (FWH0)
5 6 7 8 9 10 11 12 13
4
3
2
1
32 31 30 29 28 27 26 25 24 23 22
VDD (VDD)
A8 (FGPI2)
A9 (FGPI3)
NC
A10 (FGPI4)
R/C# (CLK)
IC (IC) VSS (VSS) NC NC VDD (VDD) OE# (INIT#) WE# (FWH4) NC DQ7 (RES)
32-lead PLCC Top View
21 14 15 16 17 18 19 20 DQ1 (FWH1) DQ2 (FWH2) DQ3 (FWH3) DQ4 (RES) DQ5 (RES) DQ6 (RES) VSS (VSS)
1161 32-plcc P2.3
( ) Designates FWH Mode
FIGURE 3: Pin Assignments for 32-lead PLCC
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7
8 Mbit Firmware Hub SST49LF008A
Data Sheet
NC (NC) IC (IC) NC (NC) NC (NC) NC (NC) NC (NC) A10 (FGPI4) NC (NC) R/C# (CLK) VDD NC (NC) RST# (RST#) NC (NC) NC (NC) A9 (FGPI3) A8 (FGPI2) A7 (FGPI1) A6 (FGPI0) A5 (WP#) A4 (TBL#)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Standard Pinout Top View Die Up
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS VDD (FWH4) WE# (INIT#) OE# (NC) NC (RES) DQ7 (RES) DQ6 (RES) DQ5 (RES) DQ4 (NC) NC VSS VSS (FWH3) DQ3 (FWH2) DQ2 (FWH1) DQ1 (FWH0) DQ0 (ID0) A0 (ID1) A1 (ID2) A2 (ID3) A3
( ) Designates FWH Mode
1232 40-tsop P1.0
FIGURE 4: Pin Assignments for 40-lead TSOP
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8 Mbit Firmware Hub SST49LF008A
Data Sheet TABLE 1: Pin Description
Interface Symbol A10-A0 Pin Name Address Type1 I PP X FWH Functions Inputs for low-order addresses during Read and Write operations. Addresses are internally latched during a Write cycle. For the programming interface, these addresses are latched by R/C# and share the same pins as the high-order address inputs. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# is high. To gate the data output buffers To control the Write operations X This pin determines which interface is operational. When held high, programmer mode is enabled and when held low, FWH mode is enabled. This pin must be setup at power-up or before return from reset and not change during device operation. This pin is internally pulled- down with a resistor between 20-100 K. This is the second reset pin for in-system use. This pin is internally combined with the RST# pin; If this pin or RST# pin is driven low, identical operation is exhibited. These four pins are part of the mechanism that allows multiple parts to be attached to the same bus. The strapping of these pins is used to identify the component.The boot device must have ID[3:0]=0000 and it is recommended that all subsequent devices should use sequential up-count strapping. These pins are internally pulled-down with a resistor between 20-100 K. These individual inputs can be used for additional board flexibility. The state of these pins can be read through GPI_REG register. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain in place until the end of the Read cycle. Unused GPI pins must not be floated. When low, prevents programming to the Boot Block sectors at top of memory. When TBL# is high it disables hardware write protection for the top block sectors. This pin cannot be left unconnected. I/O Communications To provide a clock input to the control unit Input Communications To reset the operation of the device When low, prevents programming to all but the highest addressable blocks. When WP# is high it disables hardware write protection for these blocks. This pin cannot be left unconnected. Select For the Programming interface, this pin determines whether the address pins are pointing to the row addresses, or to the column addresses. X PWR PWR I X X X X X X These pins must be left unconnected. To provide power supply (3.0-3.6V) Circuit ground (OV reference) All VSS pins must be grounded. Unconnected pins
T1.4 1161
DQ7-DQ0
Data
I/O
X
OE# WE# IC
Output Enable Write Enable Interface Configuration Pin
I I I
X X X
INIT#
Initialize
I
X
ID[3:0]
Identification Inputs
I
X
FGPI[4:0] General Purpose Inputs
I
X
TBL#
Top Block Lock
I
X
FWH[3:0] FWH I/Os CLK FWH4 RST# WP# Clock FWH Input Reset Write Protect
I/O I I I I X
X X X X X
R/C#
Row/Column Select
I
X
RES VDD VSS NC
Reserved Power Supply Ground No Connection
1. I = Input, O = Output
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
DEVICE MEMORY MAP
TBL#
Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8
0FFFFFH
Boot Block
0F0000H 0EFFFFH 0E0000H 0DFFFFH 0D0000H 0CFFFFH 0C0000H 0BFFFFH 0B0000H 0AFFFFH 0A0000H 09FFFFH 090000H 08FFFFH
WP# for Block 0~14
080000H 07FFFFH Block 7 070000H 06FFFFH Block 6 060000H 05FFFFH Block 5 050000H 04FFFFH Block 4 040000H 03FFFFH Block 3 030000H 02FFFFH Block 2 Block 1 020000H 01FFFFH 010000H 00FFFFH Block 0 (64 KByte) 002000H 001000H 000000H
4 KByte Sector 15
4 KByte Sector 2 4 KByte Sector 1 4 KByte Sector 0
1161 F08.0
FIGURE 5: Device Memory Map for SST49LF008A
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
DESIGN CONSIDERATIONS
SST recommends a high frequency 0.1 F ceramic capacitor to be placed as close as possible between VDD and VSS less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 F electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. If you use a socket for programming purposes add an additional 1-10 F next to each socket. The RST# pin must remain stable at VIH for the entire duration of an Erase operation. WP# must remain stable at VIH for the entire duration of the Erase and Program operations for non-Boot Block sectors. To write data to the top Boot Block sectors, the TBL# pin must also remain stable at VIH for the entire duration of the Erase and Program operations.
mode, the device is configured to interface with its host using Intel's Firmware Hub proprietary protocol. Communication between Host and the SST49LF008A occurs via the 4-bit I/O communication signals, FWH [3:0] and the FWH4. In PP mode, the device is programmed via an 11bit address and an 8-bit data I/O parallel signals. The address inputs are multiplexed in row and column selected by control signal R/C# pin. The column addresses are mapped to the higher internal addresses, and the row addresses are mapped to the lower internal addresses. See the Device Memory Map in Figure 5 for address assignments.
FIRMWARE HUB (FWH) MODE Device Operation
PRODUCT IDENTIFICATION
The product identification mode identifies the device as the SST49LF008A and manufacturer as SST. TABLE 2: Product Identification
JEDEC ID Address Location FFBC0000H FFBC0001H
T2.7 1161
The FWH mode uses a 5-signal communication interface, FWH[3:0] and FWH4, to control operations of the SST49LF008A. Operations such as Memory Read and Memory Write uses Intel FWH propriety protocol. JEDEC Standard SDP (Software Data Protection) Byte-Program, Sector-Erase and Block-Erase command sequences are incorporated into the FWH memory cycles. Chip-Erase is only available in PP Mode. The device enters standby mode when FWH4 is high and no internal operation is in progress. The device is in ready mode when FWH4 is low and no activity is on the FWH bus.
Byte Manufacturer's ID Device ID SST49LF008A 0001H 0000H
Data BFH 5AH
Firmware Hub Interface Cycles
Addresses and data are transferred to and from the SST49LF008A by a series of "fields," where each field contains 4 bits of data. SST49LF008A supports only singlebyte Read and Write, and all fields are one clock cycle in length. Field sequences and contents are strictly defined for Read and Write operations. Addresses in this section refer to addresses as seen from the SST49LF008A's "point of view," some calculation will be required to translate these to the actual locations in the memory map (and vice versa) if multiple memory devices are used on the bus. Tables 3 and 4 list the field sequences for Read and Write cycles.
MODE SELECTION
The SST49LF008A flash memory devices can operate in two distinct interface modes: the Firmware Hub Interface (FWH) mode and the Parallel Programming (PP) mode. The IC (Interface Configuration pin) is used to set the interface mode selection. If the IC pin is set to logic High, the device is in PP mode; while if the IC pin is set Low, the device is in the FWH mode. The IC selection pin must be configured prior to device operation. The IC pin is internally pulled down if the pin is not connected. In FWH
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8 Mbit Firmware Hub SST49LF008A
Data Sheet TABLE 3: FWH Read Cycle
Clock Cycle 1 Field Name START Field Contents FWH[3:0]1 1101 FWH[3:0] Direction IN Comments FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transitions high) should be recognized. The START field contents indicate a FWH memory Read cycle. Indicates which FWH device should respond. If the to IDSEL (ID select) field matches the value ID[3:0], then that particular device will respond to the whole bus cycle. These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. A field of this size indicates how many bytes will be or transferred during multi-byte operations. The SST49LF008A will only support single-byte operation. IMSIZE=0000b In this clock cycle, the master (Intel ICH) has driven the bus then float to all `1's and then floats the bus, prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The SST49LF008A takes control of the bus during this cycle. During the next clock cycle, it will be driving "sync data." During this clock cycle, the FWH will generate a "readysync" (RSYNC) indicating that the least-significant nibble of the least-significant byte will be available during the next clock cycle. YYYY is the least-significant nibble of the least-significant data byte. YYYY is the most-significant nibble of the least-significant data byte. In this clock cycle, the SST49LF008A has driven the bus to all ones and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The master (Intel ICH) resumes control of the bus during this cycle.
T3.3 1161
2
IDSEL
0000 to 1111
IN
3-9
IMADDR
YYYY
IN
10
IMSIZE
0000 (1 byte)
IN
11
TAR0
1111
IN then Float
12 13
TAR1 RSYNC
1111 (float) 0000 (READY)
Float then OUT OUT
14 15 16
DATA DATA TAR0
YYYY YYYY 1111
OUT OUT OUT then Float Float then IN
17
TAR1
1111 (float)
1. Field contents are valid on the rising edge of the present clock cycle.
CLK FWH4 FWH[3:0]
STR IDS IMADDR IMS TAR RSYNC DATA TAR
1161 F09.0
FIGURE 6: Single-Byte Read Waveforms
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8 Mbit Firmware Hub SST49LF008A
Data Sheet TABLE 4: FWH Write Cycle
Clock Cycle 1 Field Name START Field Contents FWH[3:0]1 1110 FWH[3:0] Direction IN Comments FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transitions high) should be recognized. The START field contents indicate a FWH memory Read cycle. Indicates which SST49LF008A device should respond. If the IDSEL (ID select) field matches the value ID[3:0], then that particular device will respond to the whole bus cycle. These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred most-significant nibble first. This size field indicates how many bytes will be transferred during multi-byte operations. The FWH only supports single-byte writes. IMSIZE=0000b This field is the least-significant nibble of the data byte. This data is either the data to be programmed into the flash memory or any valid flash command. This field is the most-significant nibble of the data byte. In this clock cycle, the master (Intel ICH) has driven the then float bus to all `1's and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The SST49LF008A takes control of the bus during this cycle. During the next clock cycle it will be driving the "sync" data. The SST49LF008A outputs the values 0000, indicating that it has received data or a flash command. In this clock cycle, the SST49LF008A has driven the bus to all then float `1's and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle." The master (Intel ICH) resumes control of the bus during this cycle.
T4.4 1161
2
IDSEL
0000 to 1111
IN
3-9
IMADDR
YYYY
IN
10
IMSIZE
0000 (1 byte)
IN
11
DATA
YYYY
IN
12 13
DATA TAR0
YYYY 1111
IN IN then Float
14
TAR1
1111 (float)
Float then OUT
15 16
RSYNC TAR0
0000 1111
OUT OUT then Float
17
TAR1
1111 (float)
Float then IN
1. Field contents are valid on the rising edge of the present clock cycle.
CLK FWH4 FWH[3:0]
STR IDS IMADDR IMS DATA TAR RSYNC TAR 1161 F10.0
FIGURE 7: Write Waveforms
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Abort Mechanism
If FWH4 is driven low for one or more clock cycles during a FWH cycle, the cycle will be terminated and the device will wait for the ABORT command. The host may drive the FWH[3:0] with `1111b' (ABORT command) to return the device to Ready mode. If abort occurs during a Write operation, the data may be incorrectly altered.
TBL# is internally OR'ed with the top Boot Block Locking register. When TBL# is low, the top Boot Block is hardware write protected regardless of the state of the WriteLock bit for the Boot Block Locking register. Clearing the Write-Protect bit in the register when TBL# is low will have no functional effect, even though the register may indicate that the block is no longer locked. WP# is internally OR'ed with the Block Locking register. When WP# is low, the blocks are hardware write protected regardless of the state of the Write-Lock bit for the corresponding Block Locking registers. Clearing the Write-Protect bit in any register when WP# is low will have no functional effect, even though the register may indicate that the block is no longer locked.
Response To Invalid Fields
During FWH operations, the FWH will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows: Address out of range: The FWH address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will be decoded by SST49LF008A. Address A22 has the special function of directing reads and writes to the flash core (A22=1) or to the register space (A22=0). Invalid IMSIZE field: If the FWH receives an invalid size field during a Read or Write operation, the device will reset and no operation will be attempted. The SST49LF008A will not generate any kind of response in this situation. Invalidsize fields for a Read/Write cycle are anything but 0000b.
Reset
A VIL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device and places the output drivers, FWH[3:0], in a high-impedance state. The reset signal must be held low for a minimal duration of time TRSTP. A reset latency will occur if a reset procedure is performed during a Program or Erase operation. See Table 17, Reset Timing Parameters for more information. A device reset during an active Program or Erase will abort the operation and memory contents may become invalid due to data being altered or corrupted from an incomplete Erase or Program operation.
Device Memory Hardware Write Protection
The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of device memory in the SST49LF008A. The TBL# pin is used to write protect 16 boot sectors (64 KByte) at the highest flash memory address range for the SST49LF008A. WP# pin write protects the remaining sectors in the flash memory. An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors. When TBL# pin is held high, write protection of the top boot sectors is then determined by the Boot Block Locking register. The WP# pin serves the same function for the remaining sectors of the device memory. The TBL# and WP# pins write protection functions operate independently of one another. Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or Erase operation. A logic level change occurring at the TBL# or WP# pin during a Program or Erase operation could cause unpredictable results. TBL# and WP# pins cannot be left unconnected.
Write Operation Status Detection
The SST49LF008A device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is incorporated into the FWH Read cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Data# Polling (DQ7)
When the SST49LF008A device is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. Proper status will not be given using Data# Polling if the address is in the invalid range.
General Purpose Inputs Register
The GPI_REG (General Purpose Inputs Register) passes the state of FGPI[4:0] pins at power-up on the SST49LF008A. It is recommended that the FGPI[4:0] pins are in the desired state before FWH4 is brought low for the beginning of the bus cycle, and remain in that state until the end of the cycle. There is no default value since this is a pass-through register. The GPI register for the boot device appears at FFBC0100H in the 4 GByte system memory map, and will appear elsewhere if the device is not the boot device. Register is not available for read when the device is in Erase/Program operation. See Table 5 for the GPI_REG bits and function. TABLE 5: General Purpose Inputs Register
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `0's and `1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop.
Bit 7:5 4 Function Reserved FGPI[4] Reads status of general purpose input pin FGPI[3] Reads status of general purpose input pin FGPI[2] Reads status of general purpose input pin FGPI[1] Reads status of general purpose input pin FGPI[0] Reads status of general purpose input pin 32-PLCC 30
Pin # 32-TSOP 6 40-TSOP 7
3
3
11
15
Multiple Device Selection
The four ID pins, ID[3:0], allow multiple devices to be attached to the same bus by using different ID strapping in a system. When the SST49LF008A is used as a boot device, ID[3:0] must be strapped as 0000, all subsequent devices should use a sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). The SST49LF008A will compare the strapping values, if there is a mismatch, the device will ignore the remainder of the cycle and go into standby mode. For further information regarding FWH device mapping and paging, please refer to the Intel 82801(ICH) I/O Controller Hub documentation. Since there is no ID support in PP Mode, to program multiple devices a stand-alone PROM programmer is recommended.
2
4
12
16
1
5
13
17
0
6
14
18
T5.3 1161
Block Locking Registers
SST49LF008A provides software controlled lock protection through a set of Block Locking registers. The Block Locking Registers are read/write registers and it is accessible through standard addressable memory locations specified in Table 6. Unused register locations will read as 00H.
REGISTERS
There are three types of registers available on the SST49LF008A, the General Purpose Inputs register, Block Locking registers and the JEDEC ID registers. These registers appear at their respective address location in the 4 GByte system memory map. Unused register locations will read as 00H. Attempts to read or write to any registers during internal Write operations will be ignored.
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8 Mbit Firmware Hub SST49LF008A
Data Sheet TABLE 6: Block Locking Registers for SST49LF008A1
Register T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK T_MINUS08_LK T_MINUS09_LK T_MINUS10_LK T_MINUS11_LK T_MINUS12_LK T_MINUS13_LK T_MINUS14_LK T_MINUS15_LK
1. Default value at power up is 01H
Block Size 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K
Protected Memory Address Range 0FFFFFH - 0F0000H 0EFFFFH - 0E0000H 0DFFFFH - 0D0000H 0CFFFFH - 0C0000H 0BFFFFH - 0B0000H 0AFFFFH - 0A0000H 09FFFFH - 090000H 08FFFFH - 080000H 07FFFFH - 070000H 06FFFFH - 060000H 05FFFFH - 050000H 04FFFFH - 040000H 03FFFFH - 030000H 02FFFFH - 020000H 01FFFFH -010000H 00FFFFH - 000000H
Memory Map Register Address FFBF0002H FFBE0002H FFBD0002H FFBC0002H FFBB0002H FFBA0002H FFB90002H FFB80002H FFB70002H FFB60002H FFB50002H FFB40002H FFB30002H FFB20002H FFB10002H FFB00002H
T6.4 1161
TABLE 7: Block Locking Register Bits
Reserved Bit [7..2] 000000 000000 000000 000000 Lock-Down Bit [1] 0 0 1 1 Write-Lock Bit [0] 0 1 0 1 Lock Status Full Access Write Locked (Default State at Power-Up) Locked Open (Full Access Locked Down) Write Locked Down
T7.3 1161
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Write Lock
The Write-Lock bit, bit 0, controls the lock state described in Table 7. The default Write status of all blocks after powerup is write locked. When bit 0 of the Block Locking register is set, Program and Erase operations for the corresponding block are prevented. Clearing the Write-Lock bit will unprotect the block. The Write-Lock bit must be cleared prior to starting a Program or Erase operation since it is sampled at the beginning of the operation. The Write-Lock bit functions in conjunction with the hardware Write Lock pin TBL# for the top Boot Block. When TBL# is low, it overrides the software locking scheme. The top Boot Block Locking register does not indicate the state of the TBL# pin. The Write-Lock bit functions in conjunction with the hardware WP# pin for blocks 0 to 6. When WP# is low, it overrides the software locking scheme. The Block Locking register does not indicate the state of the WP# pin.
PARALLEL PROGRAMMING MODE Device Operation
Commands are used to initiate the memory operation functions of the device. The data portion of the software command sequence is latched on the rising edge of WE#. During the software command sequence the row address is latched on the falling edge of R/C# and the column address is latched on the rising edge of R/C#.
Reset
A VIL on RST# pin initiates a device reset.
Read
The Read operation of the SST49LF008A device is controlled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle timing diagram, Figure 13, for further details.
Lock Down
The Lock-Down bit, bit 1, controls the Block Locking register as described in Table 7. When in the FWH interface mode, the default Lock Down status of all blocks upon power-up is not locked down. Once the Lock-Down bit is set, any future attempted changes to that Block Locking register will be ignored. The Lock-Down bit is only cleared upon a device reset with RST# or INIT# or power down. Current Lock Down status of a particular block can be determined by reading the corresponding Lock-Down bit. Once a block's Lock-Down bit is set, the Write-Lock bits for that block can no longer be modified, and the block is locked down in its current state of write accessibility.
Byte-Program Operation
The SST49LF008A device is programmed on a byte-bybyte basis. Before programming, one must ensure that the sector, in which the byte which is being programmed exists, is fully erased. The Byte-Program operation is initiated by executing a four-byte command load sequence for Software Data Protection with address (BA) and data in the last byte sequence. During the Byte-Program operation, the row address (A10-A0) is latched on the falling edge of R/C# and the column Address (A21-A11) is latched on the rising edge of R/C#. The data bus is latched in the rising edge of WE#. The Program operation, once initiated, will be completed, within 20 s. See Figure 14 for Program operation timing diagram, Figure 17 for timing waveforms, and Figure 25 for its flowchart. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.
JEDEC ID Registers
The JEDEC ID registers for the boot device appear at FFBC0000H and FFBC0001H in the 4 GByte system memory map, and will appear elsewhere if the device is not the boot device. Register is not available for read when the device is in Erase/Program operation. Unused register location will read as 00H. Refer to the relevant application note for details. See Table 2 for the device ID code.
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The SectorErase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 18 for Sector-Erase timing waveforms. Any commands written during the Sector-Erase operation will be ignored.
Write Operation Status Detection
The SST49LF008A device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ7) When the SST49LF008A device is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# pulse for Program operation. For Sector- or ChipErase, the Data# Polling is valid after the rising edge of sixth WE# pulse. See Figure 15 for Data# Polling timing diagram and Figure 26 for a flowchart. Proper status will not be given using Data# Polling if the address is in the invalid range. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `0's and `1's, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# pulse. See Figure 16 for Toggle Bit timing diagram and Figure 26 for a flowchart.
Block-Erase Operation
The Block-Erase Operation allows the system to erase the device in 64 KByte uniform block size for the SST49LF008A. The Block-Erase operation is initiated by executing a six-byte command load sequence for Software Data Protection with Block-Erase command (50H) and block address. The internal Block-Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 19 for timing waveforms. Any commands written during the Block-Erase operation will be ignored.
Chip-Erase
The SST49LF008A device provides a Chip-Erase operation only in PP Mode, which allows the user to erase the entire memory array to the `1's state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE#. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 9 for the command sequence, Figure 20 for timing diagram, and Figure 28 for the flowchart. Any commands written during the Chip-Erase operation will be ignored.
(c)2006 Silicon Storage Technology, Inc.
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8 Mbit Firmware Hub SST49LF008A
Data Sheet TABLE 8: Operation Modes Selection (PP Mode)
Mode Read Program Erase Reset Write Inhibit Product Identification RST# OE# VIL WE# DQ DOUT DIN X1 High Z High Z/DOUT High Z/DOUT Manufacturer's ID (BFH) Device ID2 Address AIN AIN Sector or Block address, XXH for Chip-Erase X X X A18-A1=VIL, A0=VIL A18-A1=VIL, A0=VIH
T8.6 1161
VIH VIH VIH
VIL
VIH
VIL VIL X X
VIH VIH
X VIL
VIH
X
X
VIL
VIH
VIH VIH
1. X can be VIL or VIH, but no other value. 2. Device ID = 5AH for SST49LF008A
Data Protection
The SST49LF008A device provides both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Software Data Protection (SDP) SST49LF008A provides the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequences. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of a six-byte load sequence. The SST49LF008A device is shipped with the Software Data Protection permanently enabled. See Table 9 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode, within TRC.
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Data Sheet
SOFTWARE COMMAND SEQUENCE
TABLE 9: Software Command Sequence
Command Sequence Byte-Program Sector-Erase Block-Erase Chip-Erase6 Software ID Entry7,8 Software ID Exit9 Software ID Exit9 1st1 Write Cycle Addr2 5555H 5555H 5555H 5555H 5555H XXH 5555H Data AAH AAH AAH AAH AAH F0H AAH 2AAAH 55H 5555H F0H
T9.6 1161
2nd1 Write Cycle Addr2 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 55H 55H 55H 55H 55H
3rd1 Write Cycle 5555H 5555H 5555H 5555H 5555H A0H 80H 80H 80H 90H
4th1 Write Cycle Data Data AAH AAH AAH BA3 5555H 5555H 5555H
5th1 Write Cycle Addr2 2AAAH 2AAAH 2AAAH
6th1 Write Cycle Data 30H 50H 10H
Data Addr2
Data Addr2
Data Addr2 55H 55H 55H SAX4 BAX
5
5555H
1. FWH Mode uses consecutive Write cycles to complete a command sequence; PP Mode uses consecutive bus cycles to complete a command sequence. 2. Address format A14-A0 (Hex), Addresses A21-A15 can be VIL or VIH, but no other value, for the Command sequence in PP Mode. 3. BA = Program Byte address 4. SAX for Sector-Erase Address 5. BAX for Block-Erase Address 6. Chip-Erase is supported in PP Mode only 7. SST Manufacturer's ID = BFH, is read with A0=0, With A19-A1 = 0; 49LF008A Device ID = 5AH, is read with A0 = 1. 8. The device does not remain in Software Product ID mode if powered down. 9. Both Software ID Exit operations are equivalent.
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Data Sheet
ELECTRICAL SPECIFICATIONS
The AC and DC specifications for the FWH Interface signals (FWH[3:0], CLK, FWH4, and RST#) as defined in Section 4.2.2 of the PCI Local Bus Specification, Rev. 2.1. Refer to Table 10 for the DC voltage and current specifications. Refer to the tables on pages 23 through 27 for the AC timing specifications for Clock, Read/Write, and Reset operations. Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA=25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Do not violate processor or chipset limitations on the INIT# pin. 2. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 3. Outputs shorted for no more than one second. No more than one output shorted at a time. This note applies to non-PCI outputs.
OPERATING RANGE
Range Commercial Ambient Temp 0C to +85C VDD 3.0-3.6V
AC CONDITIONS OF TEST1
Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 23 and 24
1. FWH interface signals use PCI load test conditions
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Data Sheet
DC Characteristics
TABLE 10: DC Operating Characteristics (All Interfaces)
Limits Symbol Parameter IDD Active VDD Current Min Max Units Test Conditions1 LCLK (FWH mode) and Address Input (PP mode)=VILT/VIHT at f=33 MHz (FWH mode) or 1/TRC min (PP Mode) All other inputs=VIL or VIH 12 24 100 mA mA A All outputs = open, VDD=VDD Max See Note3 LCLK (FWH mode) and Address Input (PP mode)=VILT/VIHT at f=33 MHz (FWH mode) or 1/TRC min (PP Mode) LFRAME#=0.9 VDD, f=33 MHz, CE#=0.9 VDD, VDD=VDD Max, All other inputs 0.9 VDD or 0.1 VDD LCLK (FWH mode) and Address Input (PP mode)=VILT/VIHT at f=33 MHz (FWH mode) or 1/TRC min (PP Mode) LFRAME#=VIL, f=33 MHz, VDD=VDD Max All other inputs 0.9 VDD or 0.1 VDD VIN=GND to VDD, VDD=VDD Max VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Max VDD=VDD Min VDD=VDD Min VDD=VDD Max IOL=1500A, VDD=VDD Min IOH=-500 A, VDD=VDD Min
T10.10 1161
Read Write2 ISB Standby VDD Current (FWH Interface)
IRY4
Ready Mode VDD Current (FWH Interface)
10
mA
II ILI ILO VIHI5 VILI5 VIL
Input Current for IC, ID [3:0] pins Input Leakage Current Output Leakage Current INIT# Input High Voltage INIT# Input Low Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 0.9 VDD 1.0 -0.5 -0.5
200 1 1 VDD+0.5 0.4 0.3 VDD 0.1 VDD
A A A V V V V V V
VIH
VOL VOH
1. 2. 3. 4. 5.
0.5 VDD VDD+0.5
Test conditions apply to PP mode. IDD active while Erase or Program is in progress. For PP Mode: OE# = WE# = VIH; For FWH mode: f = 1/TRC min, LFRAME# = VIH, CE# = VIL. The device is in Ready Mode when no activity is on the FWH bus. Do not violate processor or chipset specification regarding INIT# voltage.
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Data Sheet TABLE 11: Recommended System Power-up Timings
Symbol TPU-READ1 TPU-WRITE
1
Parameter Power-up to Read Operation Power-up to Write Operation
Minimum 100 100
Units s s
T11.2 1161
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
TABLE 12: Pin Impedance (VDD=3.3V, TA=25 C, f=1 Mhz, other pins open)
Parameter CI/O1 CIN
1
Description I/O Pin Capacitance Input Capacitance Pin Inductance
Test Condition VI/O = 0V VIN = 0V
Maximum 12 pF 12 pF 20 nH
T12.4 1161
LPIN2
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. Refer to PCI spec.
TABLE 13: Reliability Characteristics
Symbol NEND TDR1 ILTH1
1
Parameter Endurance Data Retention Latch Up
Minimum Specification 10,000 100 100 + IDD
Units Cycles Years mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78
T13.3 1161
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 14: Clock Timing Parameters
Symbol TCYC THIGH TLOW Parameter CLK Cycle Time CLK High Time CLK Low Time CLK Slew Rate (peak-to-peak) RST# or INIT# Slew Rate Min 30 11 11 1 50 4 Max Units ns ns ns V/ns mV/ns
T14.1 1161
Tcyc Thigh 0.6 VDD 0.5 VDD 0.4 VDD 0.3 VDD 0.2 VDD
1161 F11.0
Tlow 0.4 VDD p-to-p (minimum)
FIGURE 8: CLK Waveform
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Data Sheet
AC Characteristics (FWH Mode)
TABLE 15: Read/Write Cycle Timing Parameters, VDD =3.0-3.6V (FWH Mode)
Symbol TCYC TSU TDH TVAL1 TBP TSE TBE TSCE TON TOFF Parameter Clock Cycle Time Data Set Up Time to Clock Rising Clock Rising to Data Hold Time Clock Rising to Data Valid Byte Programming Time Sector-Erase Time Block-Erase Time Chip-Erase Time Clock Rising to Active (Float to Active Delay) Clock Rising to Inactive (Active to Float Delay) 2 28 Min 30 7 0 2 11 20 25 25 100 Max Units ns ns ns ns s ms ms ms ns ns
T15.3 1161
1. Minimum and maximum times have different loads. See PCI spec.
TABLE 16: AC Input/Output Specifications, VDD =3.0-3.6V (FWH Mode)
Limits Symbol IOH(AC) Parameter Switching Current High Min -12 VDD -17.1(VDD-VOUT) Equation C1 (Test Point) IOL(AC) Switching Current Low 16 VDD 26.7 VOUT -32 VDD Equation D1 mA mA mA mA mA mA 4 4 V/ns V/ns Max Units Test Conditions mA mA 0 < VOUT 0.3VDD 0.3VDD < VOUT < 0.9VDD 0.7VDD < VOUT VOUT 0.6VDD 0.6VDD > VOUT > 0.1VDD 0.18VDD > VOUT > 0 VOUT=0.18VDD -3 < VIN -1 VDD+4 > VIN VDD+1 0.2VDD-0.6VDD load 0.6VDD-0.2VDD load
T16.3 1161
(Test Point) ICL ICH slewr2 slewf2 Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate -25+(VIN+1)/0.015 25+(VIN-VDD-1)/0.015 1 1
38 VDD
1. See PCI spec. 2. PCI specification output load is used.
TABLE 17: Reset Timing Parameters, VDD =3.0-3.6V (FWH Mode)
Symbol TPRST TKRST TRSTP TRSTF TRST
1
Parameter VDD stable to Reset Low Clock Stable to Reset Low RST# Pulse Width RST# Low to Output Float RST# High to FWH4 Low RST# Low to reset during Sector-/Block-Erase or Program
Min 1 100 100
Max
Units ms s ns
48 1 10
ns s s
T17.5 1161
TRSTE
1. There will be a latency of TRSTE if a reset procedure is performed during a Program or Erase operation.
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
VDD CLK
TPRST
TKRST
RST#/INIT#
TRSTP
TRSTE TRSTF TRST Sector-/Block-Erase or Program operation aborted
FWH[3:0]
FWH4
1161 F12.0
FIGURE 9: Reset Timing Diagram
VTH CLK VTEST VTL TVAL
FWH [3:0] (Valid Output Data)
FWH [3:0] (Float Output Data)
TON TOFF
1161 F13.0
FIGURE 10: Output Timing Parameters
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
VTH CLK TSU TDH FWH [3:0] (Valid Input Data) Inputs Valid VTEST VTL
VMAX
1161 F14.0
FIGURE 11: Input Timing Parameters TABLE 18: Interface Measurement Condition Parameters
Symbol VTH
1
Value 0.6 VDD 0.2 VDD 0.4 VDD 0.4 VDD 1 V/ns
Units V V V V
T18.3 1161
VTL1 VTEST VMAX1 Input Signal Edge Rate
1. The input test environment is done with 0.1 VDD of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive than this. VMAX specified the maximum peak-to-peak waveform allowed for measuring input timing. Production testing may use different voltage values, but must correlate results back to these parameters.
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
AC Characteristics (PP Mode)
TABLE 19: Read Cycle Timing Parameters, VDD =3.0-3.6V (PP Mode)
Symbol TRC TRST TAS TAH TAA TOE TOLZ TOHZ TOH Parameter Read Cycle Time RST# High to Row Address Setup R/C# Address Set-up Time R/C# Address Hold Time Address Access Time Output Enable Access Time OE# Low to Active Output OE# High to High-Z Output Output Hold from Address Change 0 0 35 Min 270 1 45 45 120 60 Max Units ns s ns ns ns ns ns ns ns
T19.2 1161
TABLE 20: Program/Erase Cycle Timing Parameters, VDD =3.0-3.6V (PP Mode)
Symbol TRST TAS TAH TCWH TOES TOEH TOEP TOET TWP TWPH TDS TDH TIDA TBP TSE TBE TSCE Parameter RST# High to Row Address Setup R/C# Address Setup Time R/C# Address Hold Time R/C# to Write Enable High Time OE# High Setup Time OE# High Hold Time OE# to Data# Polling Delay OE# to Toggle Bit Delay WE# Pulse Width WE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Byte Programming Time Sector-Erase Time Block-Erase Time Chip-Erase Time 100 100 50 5 150 20 25 25 100 Min 1 50 50 50 20 20 40 40 Max Units s ns ns ns ns ns ns ns ns ns ns ns ns s ms ms ms
T20.2 1161
TABLE 21: Reset Timing Parameters, VDD =3.0-3.6V (PP Mode)
Symbol TPRST TRSTP TRSTF TRST1 TRSTE TRSTC Parameter VDD stable to Reset Low RST# Pulse Width RST# Low to Output Float RST# High to Row Address Setup RST# Low to reset during Sector-/Block-Erase or Program RST# Low to reset during Chip-Erase 1 10 50 Min 1 100 48 Max Units ms ns ns s s s
T21.1 1161
1. There will be a reset latency of TRSTE or TRSTC if a reset procedure is performed during a Program or Erase operation.
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
VDD
TPRST
Addresses
Row Address
R/C#
RST#
TRSTP
TRSTE Sector-/Block-Erase or Program operation aborted Chip-Erase aborted
TRSTC TRSTF TRST
DQ7-0
1161 F15.0
FIGURE 12: Reset Timing Diagram (PP Mode)
RST#
TRSTP TRST TRC
Row Address Column Address Row Address Column Address
Addresses
TAS
TAH
TAS
TAH
R/C# WE# OE#
TOE TOLZ VIH TAA TOH TOHZ
Data Valid High-Z 1161 F16.0
DQ7-0
High-Z
FIGURE 13: Read Cycle Timing Diagram (PP Mode)
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
TRSTP
RST# Addresses
TRST Row Address TAS TAH Column Address TAS TAH
R/C#
TCWH TOEH
OE# WE#
TOES
TWP
TWPH TDH
TDS
DQ7-0
Data Valid 1161 F17.0
FIGURE 14: Write Cycle Timing Diagram (PP Mode)
Addresses
Row
Column
R/C#
WE#
OE#
TOEP
DQ7
D
D#
D#
D
1161 F18.0
FIGURE 15: Data# Polling Timing Diagram (PP Mode)
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Addresses
Row
Column
R/C#
WE#
OE#
TOET
DQ6
D
D
1161 F19.0
FIGURE 16: Toggle Bit Timing Diagram (PP Mode)
Four-Byte Code for Byte-Program Addresses 5555 R/C# 2AAA 5555 BA
OE#
TWP
TBP
TWPH
WE# SB0
SB1
SB2
SB3
Internal Program Starts
DQ7-0
AA
55
A0
Data
BA = Byte-Program Address
1161 F20.0
FIGURE 17: Byte-Program Timing Diagram (PP Mode)
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Six-Byte code for Sector-Erase Operation
Addresses 5555 R/C# 2AAA 5555 5555 2AAA SAx
OE#
TWP TSE TWPH
WE# SB0 DQ7-0 AA
SB1 55
SB2 80
SB3 AA
SB4 55
SB5 30
Internal Erasure Starts
SAx = Sector Address
1161 F21.0
FIGURE 18: Sector-Erase Timing Diagram (PP Mode)
Six-Byte code for Block-Erase Operation
Addresses 5555 R/C# 2AAA 5555 5555 2AAA BAx
OE#
TWP TBE TWPH
WE# SB0 DQ7-0 AA
SB1 55
SB2 80
SB3 AA
SB4 55
SB5 50
Internal Erasure Starts
BAx = Block Address
1161 F22.0
FIGURE 19: Block-Erase Timing Diagram (PP Mode)
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Six-Byte code for Chip-Erase Operation
Addresses 5555 R/C# 2AAA 5555 5555 2AAA 5555
OE#
TWP TSCE TWPH
WE# SB0 DQ7-0 AA
SB1 55
SB2 80
SB3 AA
SB4 55
SB5 10
Internal Erasure Starts
1161 F23.0
FIGURE 20: Chip-Erase Timing Diagram (PP Mode)
Three-byte sequence for Software ID Entry Addresses 5555 2AAA 5555 0000 0001
R/C#
OE# TWP WE# TWPH DQ7-0 AA SW0 55 SW1 90 SW2
1161 F24.2
TIDA
TAA BF Device ID
Device ID = 5AH for SST49LF008A
FIGURE 21: Software ID Entry and Read (PP Mode)
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Three-Byte Sequence for Software ID Exit and Reset
Addresses 5555 R/C# 2AAA 5555
OE# TWP WE# SW0 DQ7-0 AA TWPH SW1 55 TIDA SW2 F0
1161 F25.0
FIGURE 22: Software ID Exit and Reset (PP Mode)
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1161 F26.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test
FIGURE 23: AC Input/Output Reference Waveforms (PP Mode)
TO TESTER
TO DUT CL
1161 F27.0
FIGURE 24: A Test Load Example (PP Mode)
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Start
Write data: AAH Address: 5555H
Write data: 55H Address: 2AAAH
Write data: A0H Address: 5555H
Load Byte Address/Byte Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
1161 F28.0
FIGURE 25: Byte-Program Algorithm
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Internal Timer ByteProgram/Erase Initiated
Toggle Bit ByteProgram/Erase Initiated
Data# Polling ByteProgram/Erase Initiated
Wait TBP, TSCE, TBE or TSE
Read byte
Read DQ7
Program/Erase Completed
Read same byte
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes
Program/Erase Completed
Program/Erase Completed
1161 F29.0
FIGURE 26: Wait Options
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Software Product ID Entry Command Sequence
Software Product ID Exit & Reset Command Sequence
Write data: AAH Address: 5555H
Write data: AAH Address: 5555H
Write data: F0H Address: XXH
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Wait TIDA
Write data: 90H Address: 5555H
Write data: F0H Address: 5555H
Return to normal operation
Wait TIDA
Wait TIDA
Read Software ID
Return to normal operation
1161 F30.0
FIGURE 27: Software Product Command Flowcharts
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
Chip-Erase Command Sequence Write data: AAH Address: 5555H
Block-Erase Command Sequence Write data: AAH Address: 5555H
Sector-Erase Command Sequence Write data: AAH Address: 5555H
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Write data: 80H Address: 5555H
Write data: 80H Address: 5555H
Write data: 80H Address: 5555H
Write data: AAH Address: 5555H
Write data: AAH Address: 5555H
Write data: AAH Address: 5555H
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Write data: 55H Address: 2AAAH
Write data: 10H Address: 5555H
Write data: 50H Address: BAX
Write data: 30H Address: SAX
Wait Options
Wait Options
Wait Options
Chip erased to FFH
Block erased to FFH
Sector erased to FFH
1161 F31.0
FIGURE 28: Erase Command Sequence
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8 Mbit Firmware Hub SST49LF008A
Data Sheet
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 XX Suffix2 XX Suffix3 X Environmental Attribute E1 = non-Pb Package Modifier H = 32 leads I = 40 leads Package Type N = PLCC W = TSOP (type 1, die up, 8mm x 14mm) E = TSOP (type 1, die up, 10mm x 20mm) Operating Temperature C = Commercial = 0C to +85C Minimum Endurance 4 = 10,000 cycles Serial Access Clock Frequency 33 = 33 MHz Version A = Second Version Device Density 008 = 8 Mbit Voltage Range L = 3.0-3.6V Product Series 49 = Firmware Hub for Intel 8xx Chipsets
SST49LF00xA - XXX
1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant".
Valid combinations for SST49LF008A SST49LF008A-33-4C-WHE SST49LF008A-33-4C-NHE SST49LF008A-33-4C-EIE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c)2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
38
8 Mbit Firmware Hub SST49LF008A
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
Optional Pin #1 Identifier .048 .042 .495 .485 .453 .447
2 1 32
SIDE VIEW
.112 .106 .020 R. MAX. .029 x 30 .023 .040 R. .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 BSC .490
.050 BSC .015 Min. .050 BSC .095 .075 .140 .125 .032 .026
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils.
32-plcc-NH-3
FIGURE 29: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH
(c)2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
39
8 Mbit Firmware Hub SST49LF008A
Data Sheet
Pin # 1 Identifier
1.05 0.95 0.50 BSC
8.10 7.90
0.27 0.17
12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80
0.15 0.05
0- 5 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
32-tsop-WH-7
FIGURE 30: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH
(c)2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
40
8 Mbit Firmware Hub SST49LF008A
Data Sheet
1.05 0.95 Pin # 1 Identifier 0.50 BSC
10.10 9.90
0.27 0.17
18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80
0.15 0.05
0- 5 Note: 1. Complies with JEDEC publication 95 MO-142 CD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.50
1mm 40-tsop-EI-7
FIGURE 31: 40-lead Thin Small Outline Package (TSOP) 10mm x 20mm SST Package Code: EI
(c)2006 Silicon Storage Technology, Inc.
S71161-11-000
3/06
41
8 Mbit Firmware Hub SST49LF008A
Data Sheet TABLE 22: Revision History
Revision 06 Draft Changes Date July 2001
* * * * * * *
2002 Data Book Changed Transient Voltage from -1.0V to VDD +1.0V to -2.0V to VDD +2.0V to match Intel FWH spec per IBM requirement. Added footnote for Transient Voltage. Updated footnote for Output Short Circuit Current. Updated Data# Polling description Corrected the values in Table 5 on page 15: General Purpose Inputs Register Added note to Table 10 on page 22: DC Operating Characteristics Added 40-lead TSOP for SST49LF008A only Corrected the IDD Test Conditions in Table 10 on page 22 2004 Data Book Updated document status to Data Sheet Removed 2 Mbit and 3 Mbit devices - refer to EOL Product Data Sheet S71161(01) Removed 32-PLCC (NH/NHE) Package and associated MPNs for the 4 Mbit device refer to EOL Product Data Sheet S71161(03). Clarified the Solder Temperature Profile under "Absolute Maximum Stress Ratings" on page 21 Removed 4 Mbit WH/WHE device - refer to EOL Product Data Sheet S71161(03) Added statement that non-Pb devices are RoHS compliant to Features section Updated Surface Mount Solder Reflow Temperature information Removed leaded part numbers Applied new formatting
07 08 09 10
* * * * * * *
June 2003 Dec 2003 Oct 2004 Nov 2004
11
* * * * *
Mar 2006
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com
(c)2006 Silicon Storage Technology, Inc. S71161-11-000 3/06
42

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